With recent improvement in integration, performance, and operation speed of semiconductor integrated circuit devices, a short-channel effect of transistors has become an increasingly serious problem. One of the known technologies for reducing the short-channel effect is to use a drain extension having an extremely shallow pn junction.
For example, it is said that, for a transistor having a gate electrode dimension of 65 nm, a desirable pn junction depth of a drain extension is about 13 nm. Possible technologies for implementing such a pn junction depth are a flash lamp annealing technology and a laser annealing technology in both of which the thermal budget time is suppressed to several milliseconds.
However, the heat treatment time is extremely short in such short-time heat treatment technologies. Therefore, the impurity activation ratio varies depending on a pattern on semiconductor devices, and transistor characteristics vary as a result. Such variation in transistor characteristics can be a critical drawback for mass production of system LSIs having various patterns.
In view of this problem, a technology has been proposed in which heat treatment is conducted for several minutes at a temperature that causes only activation of impurities without diffusion thereof, for example, in a temperature range from 500° C. to 800° C. This technology is called a low temperature SPE (Solid Phase Epitaxy) technology.
Hereinafter, formation of a P-channel transistor by a conventional low temperature SPE technology will be described with reference to the accompanying drawings.
FIGS. 6(a) through 6(c) and FIGS. 7(a) and 7(b) are schematic cross-sectional views showing the process of forming a P-channel transistor by using the low temperature SPE technology.
As shown in FIG. 6(a), a gate electrode 12 is first formed on a silicon substrate 10 with a gate insulating film 11 interposed therebetween. An amorphous layer 13 is then formed by implanting germanium or silicon ions on both sides of the gate electrode 12 in the silicon substrate 10 at implantation energy in the range of several keV to several tens of keV. At this time, defects 14 are generated near the interface between the amorphous layer 13 and the silicon substrate 10 that is located under the amorphous layer 13 and that has a crystal structure.
As shown in FIG. 6(b), a drain extension 15 is then formed by implanting boron ions into the amorphous layer 13 as a dopant at implantation energy of 1 keV or less.
As shown in FIG. 6(c), a halo region 16 is formed by implanting arsenic or antimony ions on both sides of the gate electrode 12 in the silicon substrate 10 at a tilt angle of, e.g., 25 degrees with respect to the normal to the substrate surface.
As shown in FIG. 7(a), a sidewall 17 is then formed on both sides of the gate electrode 12. A contact drain 18 is formed by implanting boron ions on both sides of the gate electrode 12 and the sidewall 17 in the silicon substrate 10 at implantation energy of several keV.
Finally, as shown in FIG. 7(b), heat treatment is conducted for several minutes at a temperature of 500° C. to 800° C. As a result, the crystal structure of the amorphous layer 13 is restored, and there is no longer an amorphous region in the silicon substrate 10. However, the defects 14 remain in the region that used to be the interface between the amorphous layer 13 and the silicon substrate 10.
In the above process, boron ions implanted as a dopant to form the drain extension 15 are rapidly activated in the amorphous layer 13 without diffusion during restoration of the crystal structure of the amorphous layer 13. As a result, a shallow pn junction is formed. The depth of a pn junction that is formed by this technology is substantially determined by an impurity profile that is formed right after ion implantation.
The amorphous layer 13 extends down to a level that is deeper than the pn junction of the drain extension 15. In order to form such an amorphous layer 13, the implantation energy for implanting germanium or silicon ions into the silicon substrate 10 to form the amorphous layer 13 is determined so that the entire profile of boron that is implanted to form the drain extension 15 is contained in the amorphous layer 13.
The drain extension 15 having a pn junction depth of less than 20 nm is thus formed. Since the heat treatment time is as long as several minutes, the resultant drain extension 15 has extremely low pattern dependency. The pattern dependency means that factors such as an impurity activation ratio vary depending on a pattern that is formed on the wafer surface (in a single chip). For example, when a polysilicon gate electrode is not uniformly distributed in the whole wafer, the impurity activation ratio varies due to the density difference of the distribution.    Non-patent reference 1: John O. Borland, Low Temperature Activation of Ion Implanted Dopants, Extended Abstracts of International Workshop on Junction Technology 2002, Japan Society of Applied Physics, December 2002, pp. 85-88.